In recent years, with high integration and high functionality of a semiconductor integrated circuit, the development of microfabrication technology for miniaturization and density growth of a semiconductor element is advancing. In the manufacturing of a semiconductor integrated circuit device (hereinafter also referred to as a “semiconductor device”), in order to prevent the problem such that unevenness (difference in level) of the surface of a layer exceeds depth of focus of lithography and sufficient resolution is not obtained, it is conventionally performed to flatten an interlayer insulating film, an embedding wiring and the like using chemical mechanical polishing (hereinafter referred to as “CMP”). Importance of high flattening by CMP is increasing with severer requirements of high definition and miniaturization of an element.
Furthermore, in recent years, in the manufacturing of a semiconductor device, an isolation method by shallow trench having small element isolation width (Shallow Trench Isolation; hereinafter referred to as “STI”) is introduced in order to proceed with higher miniaturization of a semiconductor element.
The STI is a technique for forming an electrically insulated element region by forming a trench (groove) on a silicon substrate and embedding an insulating film in the trench. In the STI, as shown in FIG. 1A, an element region of a silicon substrate 1 is masked with a silicon nitride film 2 or the like, a trench 3 is formed on the silicon substrate 1, and an insulating film such as a silicon dioxide film 4 is then deposited so as to embed the trench 3. The silicon dioxide film 4 on the silicon nitride film 2 as a convex part is polished and removed by CMP while remaining the silicon dioxide film 4 in the trench 3 as a concave part. Thus, an element isolation structure having the silicon dioxide film 4 embedded in the trench 3 is obtained as shown in FIG. 1B.
It is desirable in CMP in the STI that the upper surface of the silicon dioxide film 4 in the trench 3 as a concave part is flush with the upper surface of the silicon nitride film 2 as a convex part. When the degree of the flushness between the upper surface of the silicon dioxide film 4 and the upper surface of the silicon nitride film 2 is defined as flatness, a distance along a thickness (or height) direction of from the upper surface of the silicon nitride film 2 before polishing to the upper surface of the silicon dioxide film 4 as a concave part after polishing (hereinafter simply referred to as a “distance”) can provide an index showing flatness. The upper surface of the silicon dioxide film 4 as a convex part is nearly flush with the upper surface of the silicon nitride film 2, and those films are arranged on the surface having substantially same height and flatness is satisfactory, as the distance is short.
In CMP technology in recent years, not only satisfactory flatness (high flatness) but also high removal rate to a silicon dioxide film is required from the standpoint of cost, and both high removal rate and high flatness are required.
In view of the above standpoint, a method for improving polishing characteristics of a polishing agent is proposed. Patent Document 1 discloses a CMP polishing agent for flattening an interlayer insulation film, an insulating film for STI, or the like, the polishing agent including cerium oxide particles, a dispersant, a polycarboxylic acid having a weight average molecular weight of from 500 to 20,000, a strong acid (sulfuric acid) with a first dissociative acid group having a pKa value of 3.2 or less, and water, and having a pH of from 4.0 to 7.5.
However, in the polishing agent disclosed in Patent Document 1, flatness of a substrate obtained by polishing is satisfactory, but it did not say that removal rate to a silicon dioxide film is sufficiently high.
Patent Document 1: WO 2006/035771